Chip Interconnection Rules


Chip manufacturers provide Reference Designs for their chips, and their customers verify the compliance of their implementation with these recommendations. fiXtress ASR Chip Interconnection module performs this compliance check automatically. The module is a special Common Rule Test that checks the interconnection of two ICs according
to a sequence of rules. The connection check is performed between groups of pins, such as the interconnection of an ASIC to a DDR memory chip.

Logical  Schematic Review

Most DRC applications provide an abundance of false-positive errors because they focus on the visual aspects of a design (pixels/layout) and use scripts to check the design (scripts are difficult to define and require lengthy run-times).
Logical Schematic Review is based on an abundance of previously non-leveraged information that is used to add intelligence, automate the process and minimize false positives.
fiXtress Schematic Review uses the project’s BOM and Netlist (both from popular CAD applications) and predefined part libraries.
This data is used to determine whether components are connected according to proper engineering practices.
For example, fiXtress Schematic Review checks for proper input values (such as sufficient voltage, proper resistance range,sufficient capacitance and so on) and enables engineers to check for a large set of component-based errors.

Checks by BQR fiXtress Schematic Review

  • Pull-up/pull-down resistors
  • Receiver technology matching
  • Power/ground pins
  • Decoupling capacitors
  • Unconnected pins/nets
  • BOM/Netlist comparison
  • Power inputs
  • Many other automated rule checks

fiXtress  Schematic Review  – an Innovative Solution

The design of both small and large PCBs incorporates a significant number of rules, practices and technological concepts, which require a highly complex design review process.
fiXtress Schematic Review simplifies the engineering review process, reduces design time, increases design quality and automatically verifies the implementation of each company’s customized engineering design practices.
fiXtress Schematic Review enables engineers to focus on design functionality by minimizing technical errors before layout,prototyping or fabout.

schematic review flow

schematic review flow

 

Schematic Review Process Flow

BQR’s fiXtress Schematic Review is implemented throughout the design process, so that errors can be fixed at a time when making changes is easy and cost effective.
fiXtress Schematic Review uses the design BOM and Netlist as inputs. In addition, parts library models are uploaded and net names are parsed in order to obtain useful information about the design.
fiXtress Schematic Review uses all input data to analyze the design for errors.
fiXtress Schematic Review also provides an error report that is categorized by severity and details the schematic errors detected in the design. Electronic engineers can then use these reports to prioritize rectifying these errors.