Automated Schematic and Design Analysis
fiXtress Automated Schematic Review (ASR) is a patented Rule Based Logical and Parametric circuit analysis and Verification tool which automatically detects hidden design errors using BQR’s proprietary advanced algorithms. fiXtress ASR uses the design BOM, Netlist and Interconnection signals as inputs. Parts library models and parameters are uploaded and logical data such as net or pin names are used.
fiXtress ASR includes several groups of rules and after simulating the schematic it generates an error report categorized by severity, serving electronics engineers for prioritizing design corrections.
The ASR module includes 8 groups of Rules Checks
- Common Rules- a fixed set of 17 Groups while each Group includes 20 Sub-Groups (Advanced DRC).
- Connectivity Verification- Specific Rules configurable by the User using a Wizard.
- Chip Interconnect Verification- Hierarchical sequential connectivity checks between several components Busses according to a Reference Design (such as the connection of an ASIC to its DDR4 and Flash Memories, Peripherals etc.).
- Functional, Safety and Testability Rules- Specific rules that was developed for fiXtress.
- No Failure Found- NFF rules detects error, which cause the system to fail functionally without any component burning, after a reboot, the PCB works normally waiting to the next time the PCB will fail.
- ESD and Voltage Spike Rules- an important layer that checks that the internal design can protect from ESD during manufacturing.
- User Defined Rules- fiXtress include a dedicated rules editor which simplify and enhance the creation of new rules.
- Sneak Circuit Analysis- fiXtress can detect unwanted sneak circuit paths.
Common Rules – Advanced DRC (Design Rules Check)
fiXtress Common Rules includes a set of 17 Groups of checks, while each Group includes in average 15 checks. This set can be defined as a higher level of the traditional DRC (Design Rule Check) and bring mush more value to the designer.
DRC is a term used by E-CAD vendors to describe the method by which they detect design errors. Most of them mean errors in the PCB layout, and others mean simple connectivity errors or ERC (Electrical Rules Check), most of them mean checking some missing connections and rated electronic parameter, but without relations to the real operation parameter such as Power, Voltage and Current stress, which make this check non-relevant.
Connectivity Verifications are based on specific technology connectivity rules used for detecting connectivity issues such as Net name and power conflicts, ground and power supply issues, pull-up resistors on open drain outputs, etc. The rules define objects that need to be connected/not-connected and the connecting elements are customizable, using a standard Regular Expression description.
BQR has developed a pre-defined set of rules for various technologies such as: Open Drain/ Open Collector Pins, I2C, Crystal, NC pins, PCIe, deferential, PECL Terminations, Clock AC/TAC and more.
Chip interconnect verification
Digital ICs are becoming increasingly complex, with up to thousands of pins, making manual interconnection verification extremely difficult for OEM designers. To ease the task, chip vendors provide Reference Designs specifying a chip’s interconnection to its peripheral components. However, verification of the reference design’s compliance with the chip manufacturer’s reference design is also extremely difficult, due to the complexity and lack of automated tools in the CAD/EDA environment.
Functional, safety and testability rules
One of the most difficult tasks for a designer is to detect functional, safety and testability errors.
In the following schematic, we can see that the output of the chip is 2.6V, after the voltage divider the voltage drop down to 0.23V which will never turn on the LED.
Consider a chip that include several safety functions with a non-safety function. If the non-safety function will fail, it will risk the operation of the safety functions in the chip, and as a result can create a system safety disaster.
fiXtress include a wizard to help designers create new rules according to the functional product spec and authorities regulations requirements.
In most modern electronic PCBs the designer implement a Built-In Test (BIT). BIT circuits can be implemented by hardware or a combination of hardware and software. The BIT indication will provide the operator with confidence that the product is functioning correctly. If some circuits will fail, the operator will get an indication and the maintenance organization will get an indication as well and can be prepared by allocating technicians and spare parts for quick repair Turn Around Time (TAT) to bring the product to operation again. This is very important for mission critical and high availability systems.
Type of BITS:
C-BIT: Continuous BIT, which check if a function is operating correctly (example: output of a DC/DC converter).
P-BIT: Power-On BIT, which checks functions only at power-on. Those functions cannot be checked during operation (examples: memory checksum, protection circuits and communication lines).
I-BIT: Initiated BIT by the operator or technician in a non – operation mode, such as in the lab.
ATE-BIT: A set of tests that are done in the lab by using a dedicated Automated Test Equipment (ATE). This set of tests can detect failures which the previous BITs cannot detect.
Finally, fiXtress will detect all missing BIT tests and will increase the ability of the product by its self-circuits to detect and isolate failures.
No Failure Found (NFF) rules
The most common typical failure in the field is NTF or NFF (No Failure Found).
35%-70% of PCBs declared by field technicians as failed, are functional and no failure is found in the lab. This dramatically increases the number of PCBs in the pipeline, causing manufacturers large losses.
fiXtress includes special rules that can detect such errors based on the ASR module, saving time and capital.
fiXtress include a special mode in which the user can define ESD voltage levels and inject them to specific Nets. Then the tool will check if the design is robust and the protection components can protect the circuit from damage.
In addition, some components have already internal ESD protection, and then the fiXtress will check if this amount of protection is sufficient including effect of temperature.
User defined rules
In addition to all fiXtress ready to use rules, the tool includes a wizard by which the user can create new rules. The rules apply to design objects that need to be connected/not-connected, and the connecting elements are customizable, using a standard Regular Expression description.
This way the user can easily create new rules for any specific design.
The company can collect rules from all engineers, and if a junior engineer joins the team, his design will be checked against rules defined by senior engineers.
Sneak Circuit Analysis
Sneak circuits are hidden paths in the circuits which cause undesired functions to occur, unrelated to a component failure. Sneak circuits can result in an undesired operation, or in an operation at an undesired time (or both).