Automated Design Analysis and Schematic Review
fiXtress™ Automated Schematic Review (ASR) is a patented Rule-Based Logical and Parametric circuit analysis and Verification tool which automatically detects hidden design errors using BQR’s proprietary advanced algorithms.
fiXtress™ ASR uses the design BOM, Netlist and Interconnection signals as inputs, and allows users to select predefined rules or create custom rules according to their specific needs. When the simulation is done, fiXtress™ generates an error report categorized by severity, serving electronics engineers for prioritizing design corrections.
The Design Analysis module includes 8 groups of Rules Checks
- Common Rules - a fixed set of 16 Rules (Advanced DRC).
- Connectivity Verification - Specific Rules configurable by the user.
- Chip Interconnection Verification - Hierarchical sequential connectivity checks between several components Buses according to a Reference Design (such as a connection of an ASIC to its DDR4 and Flash Memories, Peripherals etc.).
- Functional, Safety and Testability Rules - Specific rules that were developed for fiXtress.
- No Failure Found - NFF rules detect errors which cause the system to fail functionally without any damages to components. After a reset, the circuit works normally until the next time this failure happens.
- ESD and Voltage Spike Rules - an important layer that checks that the internal design can protect from ESD during manufacturing.
- User Defined Rules - fiXtress includes a dedicated rules editor which simplifies and enhances the creation of new rules.
- Sneak Circuit Analysis - fiXtress can detect unwanted sneak paths in a circuit.
Design Analysis: Common Rules – Advanced DRC (Design Rules Check)
fiXtress™ Common Rules section includes a set of 16 checks. This set can be defined as a higher level of the traditional DRC (Design Rule Check), which delivers much more value to the designer.
DRC is a term used by E-CAD vendors to describe the method by which they detect design errors. Most of them mean errors in the PCB layout, and others mean simple connectivity errors or ERC (Electrical Rules Check). Mostly, these rules check for missing connections, and do not cover stress related errors that might be hidden in the design.
Design Analysis: Connectivity Verification
Connectivity Verification is based on specific connectivity rules used for detecting connectivity issues such as Net name and power conflicts, ground and power supply issues, pull-up resistors on open drain outputs, etc. The rules define, using standard Regular Expression patterns, objects that need to be connected/not-connected. The connecting elements are customizable. BQR has developed a pre-defined set of rules for various technologies such as: Open Drain/Open Collector Pins, I2C, Crystal, NC pins, PCIe, PECL Terminations, Clock AC/TAC and more.
Design Analysis: Chip Interconnection Verification
Digital ICs are becoming increasingly complex, with up to thousands of pins, making manual interconnection verification extremely difficult for OEM designers. To ease the task, chip vendors provide Reference Designs specifying a chip’s interconnection to its peripheral components. However, verification of the reference design’s compliance with the chip manufacturer’s reference design is also extremely difficult, due to the complexity and lack of automated tools in the EDA environment. The Chip Interconnection Verification tool can be used to overcome this difficult and tedious task.
Design Analysis: Functional, Safety and Testability Rules
One of the most difficult tasks for a designer is to detect functional, safety and testability errors.
Functional errors:
In the following schematic, we can see that the output voltage of the chip is 2.6V. Due to the voltage drop across the resistor, the voltage on the transistor’s base is 0.23V, effectively keeping the LED always off.
Safety errors:
Consider a chip that includes several safety functions alongside a non-safety function. If the non-safety function fails, it will risk the operation of the safety functions in the chip, and as a result might create a system safety disaster.
fiXtress includes a wizard that helps designers create new rules according to the functional product spec and authorities regulations requirements.
Testability errors:
In most modern electronic PCBs, the designer implements a Built-In Test (BIT). BIT circuits can be implemented by hardware or by a combination of hardware and software. The BIT indication will provide the operator with confidence that the product is functioning correctly. If some circuits fail, the operator will get an indication. The maintenance organization will be alerted as well. This allows to prepare by allocating technicians and spare parts for quick repair Turn Around Time (TAT) to bring the product to operation again once needed. This is very important for mission critical and high availability systems.
Type of BITS:
C-BIT: Continuous BIT, which checks if a function is operating correctly (example: output of a DC/DC converter).
P-BIT: Power-On BIT, which checks functions only at power-on. Those functions cannot be checked during operation (examples: memory checksum, protection circuits and communication lines).
I-BIT: Initiated BIT by the operator or technician in a non – operation mode, such as in the lab.
ATE-BIT: A set of tests that are done in the lab by using a dedicated Automated Test Equipment (ATE). This set of tests can detect failures which the previous BITs cannot detect.
Finally, fiXtress™ can be used to detect all missing BIT tests and increase the ability of the product to detect and isolate failures.
Design Analysis: No Failure Found (NFF)
The most common typical failure in the field is NTF or NFF (No Failure Found).
35%-70% of PCBs declared as failed by field technicians are due to functional and “No Failure Found in the lab” errors. This dramatically increases the number of PCBs in the pipeline, causing big losses for manufacturers.
fiXtress™ includes special rules that can detect such errors in its ASR module, allowing manufacturers to save time and resources.
Design Analysis: ESD and Voltage Spike Rules
fiXtress™ includes a special tool which allows the user to define ESD voltage levels and inject them to specific Nets. The tool then checks if the design is robust and whether the protection components can indeed suppress the voltage spikes.
Design Analysis: User Defined Rules
In addition to all of fiXtress™ ready to use rules, the tool includes a wizard which enables users to create new rules. The rules define, using standard Regular Expression patterns, objects that need to be connected/not-connected. The connecting elements are customizable.
Thus, the user can easily create new rules for any specific design.
Design Analysis: Sneak Circuits
“Sneak Circuit” is defined as the unexpected path or operational status in an electric or electronic circuit due to the limitation or oversight in design by human. The sneak circuit can be triggered to operate under certain conditions, which results in an unwanted or unintended action at an undesired time. This is unrelated to a specific component failure.