Shift-Left Methodology for Early Verification of Critical Electronics

Orit Buzin
Aug 12
12 min read

SUMMARY & CONCLUSIONS

By embracing a shift-left verification methodology, engineers can significantly enhance the reliability and robustness of critical electronic systems from the very start of development. The approach detailed in this paper – combining automated schematic rule checking, component derating analysis, and pre-layout stress simulation – essentially brings the rigor of later-stage testing and review into the schematic design phase. In addition, this approach identifies design flaws that could compromise mission success or safety at an early stage, permitting corrections at the schematic level rather than necessitating expensive hardware modifications. The methodology is grounded in proven best practices: it implements standard-based derating requirements, echoes the FMEA imperative of early failure mode elimination, and utilizes patented techniques for schematic and circuit verification. The expanded workflow increases the effort spent in early verification, but this investment pays off by reducing downstream problems many times over. In an era where systems are increasingly complex and failure intolerant, methods like these are becoming indispensable. As an evolving best practice, we foresee that shift-left verification flows will be integrated into standard electronic design toolchains, much as automated testing is now integral to software development.

1 INTRODUCTION

In the development of critical electronic systems (such as aerospace, medical, or automotive devices), undetected design flaws can have disastrous consequences. A single schematic error—such as the absence of a pull-up resistor or an incorrect component connection—can result in a non-functional prototype, expensive PCB re-spins, or even field failures necessitating product recalls. Traditional workflows often postpone comprehensive verification until late in the design or testing phase, when fixes are difficult and expensive. Modern design-for-reliability practices instead emphasize shifting left – performing rigorous verification as early as possible, at the schematic stage, to catch issues before they propagate to hardware. As noted in industry guidance, integrating reliability checks early in the design process contrasts with older approaches that left such checks to later stages. This shift-left mindset is driven by a simple cost-benefit truth: the earlier a bug is found, the cheaper and easier it is to fix. Catching problems during the design phase can prevent enormous costs and safety risks down the line, especially for critical systems where a late-discovered flaw might necessitate scrapping or retrofitting all produced units. To implement the shift-left paradigm for critical electronic hardware, we propose a methodology that enables early verification of reliability and robustness directly on the circuit schematic. This approach performs comprehensive automated checks and simulations before PCB layout and prototyping. It combines three key elements: (1) logical schematic verification to ensure correct connectivity and design rule compliance, component derating analysis to check that parts operate within stress limits per reliability standards [Ref. 1], and (3) deep stress simulation to evaluate component stresses and margins under worst-case conditions. By integrating these steps into the early design stage, the methodology aims to identify design issues, component weaknesses, or rule violations that could lead to failures, thereby enabling designers to fix them long before physical implementation. This paper expands on each of these elements and describes the overall verification flow. It presents a structured “shift-left” verification process tailored for high-reliability electronics, with the goal of enhancing the depth of analysis performed in the schematic phase. We also highlight how this approach aligns with recognized industry best practices in reliability engineering (RAMS), such as early FMEA and derating guidelines, and reference relevant standards supporting the method. 2 BACKGROUND AND MOTIVATION

Ensuring the reliability of critical electronics has historically involved extensive testing and analysis after a design was built – for instance, environmental stress testing of prototypes or formal failure mode analyses late in development. However, waiting until hardware testing or integration to uncover design flaws can be risky and inefficient. If a flaw originates in the circuit design itself (as opposed to a manufacturing defect), discovering it only after fabrication may require costly redesign and replacement of units in the field. In worst-case scenarios, an undetected design bug in a safety-critical system can lead to mission failure or endanger lives. Modern reliability engineering advocates for proactive measures early in the design lifecycle. Practices such as Design for Reliability (DfR) and Failure Modes and Effects Analysis (FMEA) stress early identification and mitigation of potential failure causes. The U.S. Department of Defense RAM Guide [Ref. 2], for example, notes that “the primary benefit of the FMEA is the early identification of all critical and catastrophic failure modes so they can be eliminated or minimized through design early in development.”. In other words, finding and fixing issues at the schematic or conceptual stage is far preferable to detecting them during testing or operation. This philosophy of early verification is encapsulated in the “shift-left” concept, which has gained traction not only in software testing but also in hardware design. By moving verification tasks (like design rule checking, stress analysis, etc.) to earlier phases, engineers can iterate quickly and address problems when changes are easier to implement. In the context of electronic hardware, a shift-left approach means performing pre-layout and pre-manufacturing analyses to validate that the design will meet reliability requirements. This involves using advanced Computer-Aided Engineering tools at the schematic capture stage itself, rather than after PCB layout. Early schematic reviews have been shown to catch many errors that would otherwise surface during board bring-up or environmental testing.

Additionally, by integrating reliability checks into the schematic design environment, design teams can get immediate feedback on issues like component stress or rule violations and correct them in real-time, thus significantly shortening the design cycle for high-reliability products. One industry report [Ref. 3] noted that employing automated reliability verification early can “Eliminating critical reliability errors early in the design flow can minimize complex, time-consuming verification iterations later on”. This not only improves confidence in the design’s robustness but also helps meet tight development schedules for complex systems. RAMS best practices further motivate this methodology. Standards and guides for high-reliability sectors (space, military, etc.) uniformly recommend derating components and analyzing stress under worst-case conditions during design as a means to enhance product reliability. For instance, NASA and ESA guidelines mandate derating of electronic components – i.e. using them at a fraction of their maximum ratings – to reduce the likelihood of overstress failures. The ECSS (European Cooperation for Space Standardization) specifically codifies derating requirements for nearly all EEE (electrical, electronic, and electromechanical) parts in standard ECSS-Q-ST-30-11C [Ref. 1], which must be adhered to in space hardware design. Compliance with such standards early in design avoids costly redesign if a non-compliant part is discovered later. Likewise, performing a form of stress simulation or worst-case circuit analysis during schematic design can reveal if a circuit is operating too close to the edge of its component capabilities (voltage, current, power, thermal limits, etc.), and allow redesign or component changes before any PCB is built. This approach mirrors the intent of reliability prediction models (like MIL-HDBK-217 [Ref. 4] or FIDES [Ref. 5]) which attempt to estimate failure rates based on stress – but here we integrate the prediction directly by actually calculating stress in the circuit under simulated conditions. In summary, the motivation for a shift-left verification flow is to embed reliability assurance into the early design steps, ensuring that by the time the design is ready for layout and manufacturing, it has already been vetted for logical correctness, component robustness, and compliance with reliability criteria.

3 OVERVIEW OF THE SHIFT-LEFT VERIFICATION FLOW

The following figure presents a suggested “Shift Left” flow for design of critical electronics:

Figure 1 – “Shift Left” flow for design of critical electronics

The high-level steps shown in the figure are: design the circuit function by function. For each function, the engineer conducts logical schematic verification to ensure that the components are connected correctly and not missing e.g. decoupling capacitors. Next, the engineer conducts component derating analysis to verify that the components will withstand the applied stresses. After the circuit functions have been designed and verified, a deeper analysis is conducted by stress simulation. The calculated stresses help identify additional design.The proposed verification flow consists of two complementary tool-driven stages applied during schematic design, prior to PCB layout: (A) Automated Schematic Review with Derating Compliance and (B) Pre-Layout Parametric Stress Simulation. Each stage is supported by a specialized software tool (proprietary or commercial), and together they implement a comprehensive early verification per the shift-left methodology. The process can be summarized as follows:

Stage A: ECAD-Integrated Rule-Based Schematic Verification and Derating Checks. In this stage, the schematic is analyzed against a set of design rules and reliability guidelines. The tool parses the schematic netlist and components, then applies a library of rules that encode both logical design constraints and derating requirements. This includes checking for correct connectivity, absence of common schematic errors, presence of required safety components, and ensuring that each component’s applied stress (voltage, current, power, etc.) does not exceed derated limits as defined by standard. The output is a report of any rule violations or warnings for the designer to address.Note: During this step the design engineer inputs the operational stresses for component derating analysis based on his understanding of the expected circuit behavior.
Stage B: Pre-Layout Parametric Stress and Reliability Simulation. When the circuit is complete, a more in-depth analysis can be performed by simulating the circuit’s behavior under various worst-case scenarios and design parameter extremes. Using the schematic and part models, the tool calculates the electrical values (node potentials, branch currents, power dissipation in components, etc.) across the circuit. By sweeping through corner-case conditions (such as maximum input voltage, lowest temperature, highest load, component tolerances, etc.), the tool evaluates whether components remain within safe operating limits with adequate margins. It may also calculate reliability metrics like estimated component failure rates or Mean Time Between Failures (MTBF) based on the stress results. This stage effectively serves as a “virtual stress test” of the design in the computer, before any physical prototype is built. In addition to detailed stress analysis the tool identifies design errors that may otherwise be very hard to identify (see examples in next sections).

These two stages are implemented with two distinct tools working in tandem. Tool A is typically a plugin or module integrated into the ECAD (Electronic CAD) schematic capture environment. It operates as an Automated Schematic Review (ASR) system, continuously or on-demand checking the design against rule sets. Tool B is a simulation engine (which could be integrated or standalone) that takes the schematic netlist and performs advanced analyses (electrical simulation, network solving, worst-case analysis) to predict performance and stress outcomes. The combined workflow allows an engineer to alternate between schematic entry and verification seamlessly: after drawing the circuit, they run Tool A to catch any rule violations and adjust the design, then run Tool B to see if the design can withstand extremes and adjust as needed. This iterative process continues until the schematic satisfies all verification criteria, thereby providing assurance of the design’s robustness prior to hardware. In the following sections, we delve deeper into each stage of this methodology.

4 INCREMENTAL ECAD-INTEGRATED VERIFICATION

This tool assists the electronics engineer in doing a self function by function verification for the circuit. The tool provides two types of analyses:

4.1 Logical Schematic Review

The logical schematic review is based on a set of “common rules” as well as user customizable rules. The common rules include tests for identifying floating pins, floating IC ground nets, conflicts between inputs and outputs, missing decoupling capacitors and more.The custom rules engine lets the user define rules for connectivity between object1 and object2 via a connecting element. This flexible rules engine can be customized for each company according to their design policies e.g. naming conventions for net names.A potential issue for such heuristic based rules is the occurrence of false warnings that take valuable time to review and dismiss. This issue is minimized by fine-tuning the custom rules as well as by providing the user with filtering options for the warnings.

4.2 Component Derating Analysis

Many engineers use rules of thumb during circuit design for derating, e.g. select a capacitor where the expected operational voltage is 50% from the capacitor datasheet volage rating. However, this is not enough for critical electronics that may experience high temperatures. The suggested tool accounts for derating curves which are defined per component type according to company policy or derating standard. Component rated values are kept in a library, and the tool provides methods to minimize the engineer’s work in defining the operational stresses. Once derating curves are defined, component ratings exist in the library, board temperature is defined and operation stresses are set, the derating analysis is done for the selected circuit function.

4.3 Benefits

Using such a tool provides several benefits:
Identifying design errors early in the design prevents costly design cycles and reworks.
Custom verification rules can be reused for verification of the next projects.
Operational stresses are saved as component parameters in the schematic for future reuse and for additional analyses such as MTBF prediction.
Keeping the data in the schematic increases analysis traceability.

When the circuit design is complete, before layout, a parametric stress simulation can be done:

5 DEEP STRESS ANALYSIS

5.1 Stress Simulation

The second tool is based on calculation of the component stresses such as power, voltage and current for each component. This is in contrast to the previous steps where the engineer inputted the stresses according to his understanding. Unlike a full SPICE simulation that might require detailed models and significant manual setup, this tool is oriented toward early design when not all details are fixed. It may use simplified models that allow analysis over very large circuits.This tool can identify a host of design errors that are otherwise very hard to detect.

5.2 Operation Principle

The stress calculation is achieved by the following steps:

Get BOM and NetList from the ECAD.
Define circuit inputs and output loads.
Define IC pin types and internal functions.
Define component electrical parameters in a components library.
Define state vectors where each vector entry represents the state of a nonlinear component, e.g. transistor state.
For each states vector solve the linear circuit equations to obtain current, potential and power everywhere.

When the stress calculation is complete, parametric schematic verification is done, comparing the calculated values to component voltage specs, and conducting pin level derating analysis.

6 EXAMPLES

The tools for implementing the shift left flow have been created and used for verification of circuit designs regarding leading mission critical electronics providers. Following are examples of design issues which were identified using the suggested flow and tools:

Schematic review of a circuit function revealed that I2C communication lines were accidently switched. This was identified due to violation of the following connectivity rule: pin name that includes the string “SCL” should be connected to a net name that includes the same string “SCL”. Instead, it was found that pin “SCL” was connected to net “SDA”.This would have prevented I2C communication from operating properly.
The schematic review also identified floating ground as violation of another rule: Pin name that includes the string “GND” must be connected to ground.
During component derating analysis of a function, a derating issue was identified regarding capacitor C74. The following screenshot presents this case:

Figure 2 – Component Derating Analysis

The capacitor rated voltage is 6.3V, the applied operational stress is 5V, the derating factor was found to be 60% at 25oC, therefore the operational stress should not exceed 3.78V. The tool provided a recommendation to replace C74 with a capacitor that has a voltage rating above 8.3V. The design engineer followed the recommendation and solved the issue.

Derating analysis also identified a case of over design in a space product, where the designer selected components that are too big. It was found that 3 capacitors could be replaced with smaller parts that have a lower rating, saving valuable space in the circuit while adhering to the derating requirements.
Verification based on stress simulation identified the following issue: Digital pin in IC should have a voltage that denotes ‘0’ or ‘1’, however the calculated voltage was found to be an illegal value which is between ‘0’ and ‘1’. The allowed voltage ranges for IC digital input pins were defined in the IC pin library, and compared to calculated input voltage by the simulation. The source of the error was accidental switching of voltage divider resistors.This issue could have caused erratic circuit behavior.
Another issue that was identified during the simulation-based verification was: Low voltage supply for IC. The IC power input voltage and current consumption were defined in the IC pin library, and compared to simulated value.The source of the issue was selection of a resistor with high resistance between the IC pin and voltage regulator.
After the circuit simulation, potentials are known for each circuit node and currents are known through each pin. Then pin level component derating (also known as part stress analysis) can be done. During this verification stage overcurrent was identified in the power pins of a connector. This would have shortened the product life.

7 STATE OF THE ART

Following is a comparison of the above-mentioned tools to common practices and popular tools:

Logical schematic review exists in many ECAD tools (known as ERC or DRC). However, these tools do not offer the level of rule customization which is described in this paper.
Component derating analysis is often conducted in one of two ways: rough assessment e.g. 50% derating assumption, or by using cumbersome excel sheets. The component derating suggested in this paper accounts for the detailed temperature derating curve for each component type to comply with standards such as ECSS-Q-ST-30-11C.
While circuit simulation tools such as SPICE provide detailed time domain information regarding the circuit behavior, the simulation requires many input parameters for each component, may experience convergence issues, and is limited to small circuits. SPICE is very useful for timing analysis but is not a viable solution for stress analysis in large circuits. The stress simulation tool that is suggested in this paper provides a balance between achieved accuracy and calculation effort, supporting very large circuits.
Online tools also exist where the engineer submits his design for analysis and receives a report. This has the potential of timesaving for the engineer. However, there are two potential issues with this method: 1. Data security. 2. The analysis is done remotely, and the engineer has no control over it. If the input data is incorrect or incomplete, the submit process has to be repeated. The ECAD integrated tool suggested in this paper solves these issues: data is kept locally and analysis reruns and corrections can be done in real-time.

8 CONCLUSIONS AND FUTURE WORK

A verification flow was introduced for implementing a shift left methodology in circuit verification as well as software tools for each verification step. Details were provided regarding the tools operation principles and actual examples were provided regarding circuit design errors that were identified by mission critical electronics developers using this methodology. Recent advancements in artificial intelligence and large language models present new opportunities to further automate circuit-verification processes. We plan to study the benefits and potential risks of using AI for such tasks.

REFERENCES

ECSS Secretariat, Space Product Assurance – Derating – EEE Components, ECSS-Q-ST-30-11C, Rev.2, 2021
DOD GUIDE FOR ACHIEVING RELIABILITY, AVAILABILITY, AND MAINTAINABILITY , 20095
Siemens, How can I run reliability checks early in the design cycle?
U.S. Department of Defense, MIL-HDBK-217F Notice 2: Reliability Prediction of Electronic Equipment, 1995
FIDES Group, FIDES Guide 2022 Edition A: Reliability Methodology for Electronic Systems, 2022

ACKNOWLEDGEMENTS

We would like to thank ChatGPT for providing helpful authoring tips for this paper.

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